4 SIMULATORS INC. 1 ADVANCED ELECTRONIC SIMULATION SYSTEMS 720 SIMULATOR 240 SIMULATOR 1440 SIMULATOR 480 SIMULATOR LITERATURE ON THE 120 SERIES , ■; — -^r- X.-:— ■ 1. . ■ ■ ■■■ ■ Systems Model 240 Simulator Model 480 Simulator Model 720 Simulator Model 1440 Simulator — ■■ ■■■ ■ --1 ■ ..■■-■■■;-;-.■■ ■ -v . ■■.; ■■ ■ Sub-Systems 12 PAK Sub-System, Control and Display Panel Electronic Digital Voltmeter Parallel Logic Electronic address and Servo Set Potentiometers Repetitive Operation Display Analog-Digital Computer Interface Power Supply, Type 801.0 . ■ ■ — — ■ ■ -"‘P .. . . . 'Bc. : — ' ' ■ I . 1 ■ ■■ ■ i.' 1 ■ 1 t «> Computing Components Operational Amplifier, Type 1-510 Operational Amplifier, Type 1-620 EMC Integrator Networks, 2.000 group Multiplier, Type 3.110 Co-e'Wicient Potentiometers, 7.000 group Logarithm DFG, Type 4.120 Sine-Cosine DFG, Type 4.510 Arbitrary DFG, Type 5.740 Logic Interface, 9.000 group ■ — r-« — ■■ ■■■ “j. " . ^ - --1 : ■ - — ■ — ■ ■■ Programming Aid SASI 1 Programming Method Price Sheets i - ' • ■ ■ ■■ ■ ■ ■ ' System and Component Price Sheets SIMULATORS INC. 3611 Commercial Drive Northbrook, Illinois 60062 • Phone (312) 272 6310 PRODUCT DATA SYSTEM EVALUATION THE 240 SIMULATOR d pA£>ci64mt cj^em^ioL aHalo<^ co^npMten^ THE 240 SIMULATOR is a precision general purpose analog computer. Of an all silicon solid state design, the unit applies a modular construction to obtain a combination of high perform- ance and flexibility. A sound fundamental technical design coupled with some unique packaging techniques offers the 240 Simulator user a choice of computing networks, accuracies and features to suit a wide range of applications. A DESK TOP COMPUTER, the 240 Simulator has an expanded capacity of 28 operational amplifiers and a complete line of associated linear and non-linear computing components. The unit has features, accuracies and capabilities normally asso- ciated only with large simulation systems. The small size with large system features makes the 240 Simulator an ex- cellent educational computer for the teaching of modern simula- tion principles. RELAY RACK MOUNTING capabilities allow the 240 Simulator to be easily integrated Into an instrumentation laboratory. The wide range of available networks, the flexibility in equipment selection, and the numerous trunk lines establishes the unit as a capable general or multi-purpose instrument. EXPANDABILITY is one of the major design criteria. The 240 Simulator benefits in being a member of the Simulators, Inc. Series 120 Advanced Electronic Simulation Systems, where within the series all components and most assemblies are physically interchangeable. The 120 family includes the 240, 480, 720 Simulator and 1200 Simulator. The 240 Simulator, by virtue of the 120 Series approach, may be expanded beyond the full equipment complement. A Simulators, Inc. trade-in policy allows low cost expansion to any 120 system. The purchaser, through the trade-in value, is able to obtain the most computing capability for a limited budget with full regard for expansion. PROGRAMMING considerations play a large part in the 240 Simulator's overall ease of operation. The patch panel layout is based on a 1 2 amplifier group identified as the 12 PAK sub- system. Patching for all standard 12 amplifier groups is identi- cal, thus the 240 Simulator is programmed essentially the same as all other Series 120 systems. Operational elements are color coded and arranged to follow normal analog computer program diagrams. In addition the SASI I (Software for Analog Simula- tion) programming aid is offered to complement the patching layout. SASI I assists the user in allocating equipment, patch- ing, program scaling and general housekeeping. Programming concepts incorporated in the 240 Simulator are an asset to both the novice and experienced programmer. MAXIMUM EFFICIENCY of problem run time is encouraged with the 120 Series approach to program setup and checkout. Every known feature has been Implemented to eliminate the incon- venience and errors produced from post patching. Static check references are available at the patch panel. Integrator deriva- tives may be monitored through system address. Empirical functions are set independent of the patched program by use of a setup unit. Also co-efficient attenuators may be set externally by a digital voltmeter through use of the address buss. Efficien- cy or problem solution is a definite 240 Simulator design cri- terion. HYBRID COMPUTING considerations are everywhere apparent in the 240 Simulator. Electronic mode control with the optional feature of electronic hold, electronic switching of summers, track-store units, and high speed comparators all aid in hybrid and iterative problem solution. The Simulators, Inc. electronic digitally set attenuators are available as a standard system feature. The 240 Simulator is well prepared to implement hybrid computing techniques. STANDARD EXPANDED SYSTEM CONFIGURATION 24 12 24/30 2 12 4 4 4 2 4 2 4 13 26 ea. Operational Amplifiers w/summer Inverter networks ea. Borrowable summer networks ea. Co-efficient Potentiometer ea. Electronic Digitally Set Attenuators ea. EMC Integrator Electronic Switching or Track Store Networks ea. Multiplier Networks ea. Fixed DFG Networks ea. Arbitrary DFG’s (amplifier included) ea. Comparator Amplifiers ea. Active Limiters ea. 3 pole Double Throw Function Relays ea. Push Button Function Switch ea. Trunk Lines 3611 COMMERCIAL DRIVE • NORTHBROOK, ILLINOIS 60062 • (312) 272-6310 Current general purpose analog computers find increasingly diverse applications In widely varying scientific disciplines. Modern equipment needs impose a demand for flexibility in problem solving capability, system size and distribution of components. Simulators, Inc. has approached this difficult flexibility requirement through packaging the 240 Simulator in a modular construction. Computing components are housed In a four amplifier module (shown to the right) which, for perform- ance considerations is positioned directly behind the patch panel. An assortment of available modules allows the user to select computing networks for a best fit of specific require- ments. The removable modules are integrated Into the system through the use of high quality connectors. High impact resis- tant orlon-filled diallyl phthalate block forms the patch bay. Removable computing components are installed into the module. A removable pre-patch panel provides the means for analog computer program storage. A standard feature in all 240 Simula- tors, the patch panel is composed of a high dielectric diallyl phthalate selected for its low leakage characteristics. Gold plated patch cord tips mate with gold plated patch bay contacts. A wiping action Imposed by the patch panel receiver design insures a positive low resistant contact. Patch bay contacts have a low angle of Incidence and a wide blade to operate well with both prepatched programs and post patching. Patch panels are attractively color coded and are available to the user at the lowest possible cost. The 240 Simulator power supply design, the type 801.0, is a masterpiece of engineering for high performance and minimum maintenance. Of an all silicon design, the unit will withstand ambient temperature to 130° F. The wiring harness is layed out so that all test points are readily available for trouble shooting. Interchangeable regulator boards mounted in a printed circuit card file provide the maximum in maintainability. And even low cost protection is considered. The fuses are of the readily available inexpensive types commonly found in radio parts supply shops. The 240 Simulator's maintainability is further accented by the ease of access to every component. In addition to the remova- ble back plate, both side and top panels are easiKy removed. The side skin removal enables an access to every cubic inch in the system. Located directly under the top panel, integrating capacitors may be adjusted while the Simulator is in a standard operating configuration. The 240 Simulator is a compact deslgn- yet high in maintainability. CONTROL AND DISPLAY PANEL -r SECTOR M ! 1 » 3 4'’S^S 7 a 9 10 11 12 r-; — :r~»*^cYOR a — — 1 1 a' 3 4 8<-‘a .7 a 9 io ii la ' COM»»A«ATO«S - - 12 3 4 OVERLOAD o w VOLTWeTER *<1, t MAI MW S SELECTOR SIMULATION GROU P Sil M , “flRT . 1 Hi ■ I mu f MODE CONTffOL SPECIAL EMNCTIONS ^ t ^ U VI ' t- ■' f «r :;V A^ - vi ADDRESS The 240 Simulator control and display panel presents a sophisticated push button control of system operations. Considerations for monitor, address and control appear on the panel from left to right, top to bottom, as follows: MONITOR OVERLOAD INDICATORS. The upper left position is the dis- play for individual amplifier overload and comparator state indicators. Color coded lamps clearly indicate the overload status of all 24 system amplifiers and the two amplifiers committed for precision positive and negative reference. Also a light indicator for each comparator shows the existence of a ** \ ** condition. VOLTMETER. A ±50ua sensitivity voltmeter is used to moni- tor power supplies and all system operational elements as either a DC voltmeter or nullmeter. VOLTMETER SELECTOR. A rotary switch selector provides both monitor selection and voltmeter ranging. The table below shows the 12 selector positions and the full scale voltmeter needle deflection. Position Mode Position Mode Address x 1 Voltmeter Address x 1 0 Voltmeter Balance Voltmeter Pot Null + Nul Imeter Neg Null - Nul Imeter Ref. Bal. Voltmeter +30 Voltmeter + 15 Voltmeter - 15 Voltmeter RV Voltmeter + 10 Voltmeter - 10 Voltmeter Function Monitor of address buss Monitor of address buss Monitor of address buss Monitor of address buss Monitor of address buss Monitor of pos. & neg. ref. Monitor of +30v power sup. Monitor of + I 5v power sup. Monitor of- I 5v power sup. Monitor of Relay power sup. Mon itor of + I Ov Reference Monitor of- I Ov Reference Full Scale Range (±) lOv I V 50 mv 50 mv 50 mv 50 mv 30v 30v 30v 30v lOv lOv EXTERNAL Each 240 Simulator has a 21 pin connector located at the units rear. Output terminators are provided for external monitor of power supplies and the address buss. Reference, signal and relay ground and slave connectors are also available. The connector forms a convenient means of system output to read out equipment. SIMULATION GROUP The Simulation Group is a unique application of a chopper stabilized amplifier to a number of useful functions. The rotary switch control avails the user the following: HSRO High speed repetitive operation control. Compute or operate timing unit is controlled by the Null Pot. The SG amplifier sweeps a ramp of -10 to +10 that may be used as a display oscilloscope time base. RAMP The SG amplifier is programmed as a time base integrator with a -10 to +13.5 volt linear ramp out- put. 1C and OP are controlled from the ‘‘slow time*’ mode control, the ramp slope a function of the null pot setting. Output may be used as an XY plotter or oscilloscope time base. DER .1 The SG amplifier is used to monitor integrator derivatives and the electronic digitally set attenu- ator. The .1 scaling is a convenient readout of derivatives equivalent to ±10 - ±100 volts value. DER I Same as above except I scaling Is for derivatives of values less than ±IOv. STFS The SG amplifier is programmed as a static func- tion generator setup unit independent of the patch panel. Through use of the null pot and SG amplifier a manual sweep of -10 to +10 volts serves as the ADFG Input. Read out of the function Is conven- iently obtained through an XY plotter or DVM. ROFS “RO” indicates a rep op ADFG setup for use with the oscilloscope display. A -10 to +10 ramp from the rep op timing unit is used as the ADFG input. The entire ADFG function may be displayed for setup purposes. ADDRESS The 240 Simulator address is a 24 position rotary switch that provides' address for amplifier outputs, potentiometer wiper arms, trunk inputs, integrator derivatives, ADFG outputs, and the electronic digitally set attenuators. A selector switch identifies the function and the 24 position rotary switch selects the unit. Address is by function, sector and unit. MODE CONTROL The 13 lighted push buttons are used to control system opera- tions and special functions. From left to right the operation of each push button Is described as follows: POWER PATCH 1C HD OP REP. OP. . IB SLAVE ST. CK. I lOv 60cps AC power switch for ail power suppi ies. Energizes balance and pot set buss. All patch panel inputs to amplifiers are separated from the amplifier and grounded. Amplifiers are In the high gain balance configuration. Patch panel reference terminations are deactivated. Potentio- meter inputs are removed from the patch panel program and connected to the 10 volt reference for setting co-efficients. Slowtime initial condition Integrator mode control, momentary “feather touch** type push button. Slow time integrator hold mode control. May be used for relay or electronic hold. Momentary type push button. Slow time integrator operate mode control Momen- tary type push button. Energizes repetitive operation time scale buss and enables rep op timer. Console time scale provisions. All integrator time scales increased by 10 factor in both slow time or repetitive operation. The 240 Simulator is made the slave of a master unit. Static check mode for program check procedures. Static check reference placed to specific patch terminations only in this mode. SPECIAL Push buttons may be used: as analog function FUNCTIONS switches (single pole double throw terminations at the patch panel); to activate a function relay; or for other functions such as an enable for automatic hold in overload. CONTROL OPERATIONS AMPLIFIER BALANCE. Balance potentiometers for all 24 amplifiers are located under the decorative flap at the control panel. To balance an amplifier the voltmeter selector is placed In the ‘’"BALANCE*’" position. The amplifier is addressed and nulled to a balanced condition. attenuator setup. In the patch mode all potentiometer inputs are removed from patch panel terminations and switched to positive reference. The '"POT NULL” position of the volt- meter selector arranges the voltmeter as a positive nullmeter. Potentiometers are addressed and nulled to the "‘'NULL POT” setting. REP OP COMPUTE TIME CONTROL. The "‘’NULL POT” controls compute time for the “REP OP” mode. Compute time varies inversely with the ""NULL POT” setting, a unity setting equals I 0 ms. OUTLINE OF FEATURES MODE CONTROL Push button illuminated momentary and alternate action switches. MONITOR 50u amp voltmeter furnished with the system. Address de- signed for DVM monitor. Ample trunks for other readout equipment. Individual amplifier overload and comparator state indicators are provided. ADDRESS Rotary switch address of amplifiers, potentiometers, trunks, ADFG's, Digitally set attenuators and integrator derivatives. OPERATIONS Patch mode for amplifier balancing, program patching, attenuator setup, and patch panel removal. Repetitive Operation Mode for oscilloscope display of problem solutions. (75 solutions per second maximum rate) Ramp output from Simulation Group amplifier used as os- cilloscope time base. Console Time Scale for increasing time scale of all integra- tors by I 0 factor. Static Check Mode for ease of static check procedures. Slave Mode for control of the slaved 240 Simulator by a master computer or device. Derivative monitor of all integrators. Derivative readout through the Simulation Group Amplifier In HD and 1C or HD and OP mode. Function Generator Setup Unit allows ADFG to be set up independent of the patch panel input. A function may be set up statically through use of a plotter or DVM, or In repetitive operation through use of an oscilloscope. PERFORMANCE POWER SUPPLY- 1 75 watt unit may operate 64 amplifiers. All fuses inexpensive, easy to replace. RE FERENCE-Positive and negative 10 volts, 300 ma output each. .01% regulation with .005% tracking. Monitor of posi- tive and negative reference balance. PATCH PANEL-Gold plated cords mate gold plated patch bay contacts with good wiping action. AMPLIFIERS-AII silicon solid state, low offset, low noise, short time recovery from overload with good dynamic characteristic. ADFG SETUP. ADFG’s may be set statically where a DVM or plotter is used to monitor input and output - or dynamically through useof the repetitive operation oscilloscope. All ADFG's have a toggle switch that removes the patch panel input and places the input on the SIMULATION GROUP amplifier output buss. In the static setup the ADFG input is determined by the NULL POT setting. The SG amplifier varies linearly with the NULL POT from -10 to +10 volts. The ADFG outputs may be monitored through the system address. The rep. op. setup uti- lizes a repetitive operation sweep as the ADFG input where the ADFG output may be monitored for a overall visula display of the empirical function. LIMITER SETUP. Active limiter potentiometers are located under the decorative flap alongside the balance potentiometers. A positive and negative pot is supplied. The amplifier to be limited Is monitored for desired limit conditions. DERIVATIVE MONITOR. When the 240 Simulator is in the HD mode, the address function selector positioned to ""Derivative” and the SIMULATION GROUP positioned to either DER I or . I , (depending on derivative value), the inverted integrator deriva- tive will appear on the address buss. Readout may be through the nullmeter or external device. INTEGRATORS-ElectronIc mode control. Electronic hold option. Up to 5 times scales per integrator available. All adjustable polystyrene capacitors. ATTENUATORS-Compositlon or wire wound option. Wire wound 5K ohm resistance, .01% resolution. MULTIPLIERS-To .013% FS accuracy. Exceptional small signal accuracy. Good dynamic characteristics. ARBITRARY DFG's-IO segment variable slope, variable break point, switch for parallax. Gain and initial slope adjustment. Adjustments have knobs w/indicator and scale setting. COMPARATORS-H Igh sensitive amplifier with digital output and complement. L IMITERS-Active hard limit. Positive and negative potentio- meters furnished with each unit. PROGRAMMING SASI 1 (Software for Analog Simulation I) programming aid and training kit furnished to 240 Simulator users. MAINTENANCE CONSIDERATIONS Modular construction Removable Top & Side Panels All silicon solid state components, no germanium used All electronic components distributor catalog items. No hous numbers. FIELD SERVICE REPLACEMENT PROGRAM Practically all 240 Simulator maintenance may be handled through the Replacement Parts Program. Should a component be inoperative, the user notifies the Simulators, Inc. factory to rush, within 24 hours, a replacement part. The user keeps the replacement part, which will have been refurbished to new equipment standards, the defective part retained by Simulators, Inc. WARRANTY All 240 Simulators are furnished with a full one year warran- ty. Simulators, Inc. will repair under the Replacement Parts Program, at no cost to the user, any cause of defective oper- ation. The one year warranty covers all normal operation; however, excludes obvious operator abuse to the system. SIMULATORS INC. 3611 Commercial Drive Northbrook, Illinois 60062 Phone (312) 272-6310 i' SIMULATORS IIMC PRODUCT SYSTEM EVALUATION 12 PAK SUB SYSTEM DESCRIPTION THE 12 PAK SUB SYSTEM is a 12 amplifier group of analog computing components common to all Simulators, Inc. Series 120 Advance Electronic Simulation Systems. It is a complement of equipment selected for a flexible, well rounded distribution of operational amplifiers and their associated linear and non- I inear networks. AS A SECTOR of the 120 Series Simulators the 12 amplifier group provides a series identity and a common patching layout for both small and large systems. Operational element loca- tions and patching are standard for all systems. The approach has the advantage of facilitating initial orientation to any of the 120 systems as well as providing a convenient breakdown of components for programming ease. ALL SERIES 120 SIMULATORS are multiples of the 12 PAK sub-system. The 240 Simulator has two each 12 PAKs, the 480 Simulator-four each 12 PAKs and the 720 Simulator has six each I 2 PAKs. ADDRESS of a computing component or trunk lines is one of sector or 12 PAK identification and address of the unit within the sector. For example amplifier 3 of Sector 2 Is addressed A2/3. Pot 12 of Sector 5 would be addressed P5/I2. THREE NETWORK AND COMPONENT MODULES comprise the 12 PAK sub-system. The modules house four amplifiers, computing networks and summing resistors, as well as provide feed-throughs for trunks, attenuators, ADFG's, etc. There are two basic modules with variations for packaging flexibility. The standard 12 PAK complement incorporates two identical modules having integrator and multiplier provisions for ampli- fiers 1-4 and 9-12. The middle module, amplifiers 5-8, contains a logic Interface and the fixed diode function generators. The computing components may be allocated as follows: STANDARD 12 PAK CONFIGURATION 4 ea. Summer- Integrators 2 ea. Summers w/electronic switching 6 ea. Summer-Inverters I 2 ea. Co-efficient Potentiometers 1 ea. Electronic digitally set attenuator 2 ea. Multipl iers 2 ea. Arbitrary Diode Function Generators with included amplifiers 2 ea. Fixed Diode Function Generators 1 ea. Comparator 2 ea. Track and Store Units I ea. 3 pole double throw function relay & driver 1 ea. Function switch terminations 2 ea. Hard Limiters 4 ea. Free Diodes 13 ea. Trunk I ines 12 PAK SUB-SYSTEM TOO yihKio njilM MOOT i-Qf--- > I 2 PAK SECTOR ON PATCH PANEL ALTERNATIVES TO STANDARD CONFIGURATION 2 ea. Summer-Integrators may replace the summers w/elec- tronic switching 1 ea. Multiplier may replace 2 ea. Fixed diode function generator 2 ea. Fixed diode function may replace I ea. Multiplier 6 ea. Co-efficient potentiometers may replace 13 trunk I ines 2 ea. Summers may replace 2 ea. Summer- integrators 3611 COMMERCIAL DRIVE • NORTHBROOK, ILLINOIS 60062 • (312) 272-6310 impl ifier A I sistor input values al condition, integrator A5 patched to FDFG Positive, negative reference and signal ground located at the top row of all modules Reference appears only in the static check mode lOOK feedback (patched for summer- inverter operation) as inverter for use with divider, I OK feed back 1C becomes summer input, gain of I 2 as summer With I OK patched feedback Denominator +x, -x Borrowable network patched to A6 Divider numerator inputs Multiplier patched to A 10 as divider AM as Summer using 1C resistor as feedback IN RESET O SJ COUNT o DIGITA L POT’X w Storage capacitor for Track & Store application Switch controls removed for summer mode Diagonals indicate relay ground Digital pot will clear with logical “I Digital pot will count with logical **l Electronic switch controls A7, A8 OP buss (complement of above) Comparator compares 2 Input signals, + comparison outputs logic level at the “T* termination, **0" outputs the complement Function relay driver (energized by logic level) SIMULATORS INC 3611 Commercial Drive Northbrook, Illinois 60062 Phone (312) 272-6310 s patched for integrator configuration 9 12 PAK PATCHING The standard 12 PAK layout is illustrated as a quick reference for the patching of commonly used operational elements. Fur- ther details may be found on individual computing component data sheets. Limiter I A patched to lirr Attenuator input Attenuator output SJ termination indicates summing junction A I patched as inverter (I OK feed back) Inputs to multiplier Multiplier output is A2 Multiplier uses lOK feed back Summing' input to multiplier (xy +Z function) Multiplier summing junction ADFG input and output (no amplifier req*d.) Free diodes (may be matched as zero limiter) x2 Relay (programs multiplier into 2 ea. x2 DFG’s) Integrator time scale relay (controls integrators A3, A4) Console time scale buss Rep. op. time scale relay (controls Integrators A3, A4) rThe 10 and 100 indicatej Borrowable network f patched to A3 / I scM P3 P4 /^C y P/^ P/ o o / T1 T2/ T3 d 0/0 o '/ OUTPl^TRUNKS / T1 / T2 T3 > ^ Jo O 0 T^NPUT trunks kC 100 100 100 100 LIM A FDFG 100 1(70 100 100 ISJ* b ( A2 MULT. 100 100 FDFG 10^ SJ*!^ ^j! functio^^witc ort> d 9Xb_ds F|)FG FUNCTION RILAY I I a Id) RQr— )H3 /S5'>^4 EST Oo IN2 CO MPA RELAY T SC#^E CONTROL DRIVE! FDFG networks Rep. op. time scale buss Hold Buss Hold control for A3, A4 EMC OP mode control buss Integrators 1C & OP mode control Netv W>.r-VV.X; SIMULATORS IIMC PRODUCT DATA C O M P IJ T I > (; CO M P O N E N T OPERATIONAL AMPLIFIER, TYPE 1.520 FEATURES Silicon Solid State Design Solid State 400 cps Chopper High Current Output Excellent Capacitive Loading Characteristics Low Summing Junction Offset Short Time Recovery from Saturated Overload Low phase shift at high frequency operation Excellent overall dynamic characteristics Low 60 cps pick-up High signal-noise ratio drive _ E OUT DESCRIPTION SIMPLIFIED SCHEMATIC OF THE TYPE 1.520 DC OPERATIONAL AMPLIFIER THE TYPE 1.520 OPERATIONAL AMPLIFIER is a high per- formance solid state design of a quality to excel in the widely varying requirements of modern analog and hybrid computing. A sound basic approach and some unique circuitry provides both accurate low drift slow time and excellent high frequency oper- ation. The 1.520 amplifier blends gain and roll-off with out- standing chopper stabilization to yield exceptional system performance. LOW FREQUENCY or slow time simulation is traditionally the analog computer’s major function. Accurate differential equa- tion solution is primarily dependent upon the computer’s low frequency (.1 to 10 cps) performance. An analog system must have an operational amplifier that delivers high uniform gain, low phase shift, a large signal to noise ratio, low summing junction offset while maintaining good stability throughout the low frequency range. The 1.520 amplifier has been carefully designated to meet precision slow time computing criteria. CHOPPER STABILIZATION effectively eliminates DC ampli- fier drift. Its use, however, can have undesirable side effects. If the stabilizer section has a large time constant, it inherently produces a large low frequency phase angle. The result is an unexpected slow time gain loss and phase shift increase. To reduce the demodulator time constant, an amplifier must employ a high frequency stabilizer. The 1.520 amplifier applies a 400 cps chopper to absolutely minimize slow time computing errors. 400 CPS CHOPPER FREQUENCY also serves to reduce 60 cps pick-up. The stabilizer operates at the desirable seventh harmonic of the ubiquitous AC power frequency. Beat with and pick-up of 60 cps spurious signals is almost eliminated In the Type 1 .520 ampi Ifier, THE SOLID STATE CHOPPER enables the stabilizer to oper- ate at high frequencies without the reliability problems of a mechanical chopper. The solid state chopper employed in 1.520 amplifiers is precisely controlled by a timing sequence that best suits stabilizer operation. LONG TIME RECOVERY from overload conditions Is both a nuisance and handicap to the analog computer. The 400 cps chopper frequency, along with a unique stabilizer limiting cir- cuit, provides the 1.520 amplifier a fast return from saturated overload.’ HIGH INPUT IMPEDANCE to the DC and stabilizer sections Is imperative for low amplifier input current. As Input current is critical to the amplifier’s application as an integrator, mini- mum Input current has been a major criteria for the 1.520 de- sign. The unit uses a differential Input stage, a low leakage blocking capacitor and high stabilizer input impedance. The 1.520 amplifier provides unsurpassed performance as an analog computer integrator. AMPLIFIER BALANCE or the adjustment of summing junction offset directly effects the ampI Ifier’s performance as an inte- grator. A poor balancing technique results in undesirable inte- grator drift. In all Simulators, Inc. systems the 1.520 ampli- fiers are balanced in a high gain configuration (large feedback resistance), the only method to absolutely minimize summing junction offset. CAPACITIVE LOADING characteristics provide an indicator of an amplifier’s stability in system operation. Marginal capa- citive loading capability may result in amplifier oscillations. Distributed capacitance loading on both the summing junction and output and the amplifier used as an electronic mode con- trol Integrator may cause a decided loss of performance. The 1 .520 amplifier exhibits a stability that Insures uniform accura- cies under relatively severe capacitive loading. EXCELLENT DYNAMIC ACCURACIES are a feature of the Type 1.520 design. Open loop gain at the IKC operating range is maintained at a high level. Phase shift Is such that gain and phase shift errors are compatible. Compensation of input and feedback networks are not required allowing for consistant accuracies with widely varying patching configurations. OVERALL the Type 1.520 operational amplifier Incorporates every known technical advance to provide analog and hybrid computing the highest level of performance. 3611 COMMERCIAL DRIVE • NORTHBROOK, ILLINOIS 60062 • (312) 272-6310 ELECTRICAL CHARACTERISTICS % TEST PROCEDURE \ OPEN LOOP GAIN Frequency response characteristics of an operational ampli- fier provide an insight to the amplifier’s stability as well as performance in high frequency operation. The classic roll-off slope of 20 db/decade indicatesthat the circuit is essentially first order with little tendency toward oscillation or peaking. The 1.520 amplifier frequency response follows closely the 20 db/decade slope while maintaining the gain required for high speed computing. The 74 db gain at the IKC operating range yields a gain error of less than .015%. Open loop gain may be obtained through the above test setup. The ratio of input less output divided by input shows the closed loop error due to open loop gain loss. Open loop gain (in decibels) is approximated from its reciprocal to be 20 log Ein-Eo. lOCPS lOOCPS IKC lOKC lOOKC FREQUENCY PHASE SHIFT As a rule, phase shift is the most limiting factor to accurate high frequency operation. For example, a phase angle of . 1° has a sine or error of .3%. Phase shift is a function of ampli- fier design, system packaging, and network impedances. The illustrated phase angle vs frequency curves are for the Type 1.520 amplifier as packaged in all Simulators, Inc. systems. Input and feedback resistors are the Simulators, Inc. stand- ard, and as with all standard Simulators, the resistors are uncompensated. Curves are from data measured at the patch panel with the amplifier patched as an inverter. The above circuit may be used to measure phase shift. A sine wave input to the amplifier under test is also summoned with the amplifier output. A lissajous figure of error vs. sine wave input will display phase angle error. The error may be meas- ured at the Y axis where x=0 or 180°. Phase angle is the arc sine of error ^ input. Care must be taken to match impedances of RA and RB else any discrepancy may be interpreted as amplifier phase error. RA and RB should be reversed and the two readings averaged. FREQUENCY Attention is called to the monotonic characteristic of the of the above phase shift curves. Phase shift is shown to in- crease with frequency at close to a constant rate, an Indica- tion of sound amplifier design and packaging techniques. ft ELECTRICAL CHARACTERISTICS TEST RESULT 2v K- INPUT i^ - | TEST PROCEDURE TOTAL DYNAMIC AMPLITUDE ERROR The overall dynamic amplitude error is a combined phase shift and gain error. It is generally specified at the I KC fre- quency operation with the amplifier patched as an inverter. Total dynamic amplitude error may be found from the same lissajous figure used to determine phase shift. Where phase shift is measured only at the Y axis (the input sine wave being 0° and 180°), total dynamic error is the maximum error amplitude that may occur over the entire input range. VELOCITY LIMIT Velocity limit is the maximum rate at which an amplifier may pass a signal. It is generally expressed in volts/sec. and indicates to the user a high frequency operating limit for full scale use of the system. A saw tooth wave input to an amplifier patched as an inverter will provide a quick velocity limit check. Holding a constant frequency the saw tooth amplitude is increased until a limit is detected. NOISE Amplifier noise is an undesired complex output superimposed on normal operating signals. Its origin is mainly from circuit components, power supply and ground noise, and chopper drive. Characteristics may be listed in both RMS (root mean square) and/or peak amplitude, referred to the running junction. The RMS specifications are preferred by many manufacturers as their values may be considerably lower than those given for the same amplifier In peak noise figures. Also RMS specifi- cations may hide relatively large narrow spikes (such as those resulting from the chopper). Both RMS and peak noise specifications are listed for the 1.520 amplifier to show that chopper spikes do not exert a noticeable influence on the amplifier performance. To fully evaluate the effect of noise on system accuracies, it Is necessary to analyze the frequency components that comprise the overall wave form. By use of simple filters, it is possible to place various band widths on an oscilloscope. These may be photographed as shown on the attached 1.520 noise measurements. TIME -*|lusec|-^- 0-500kc -H k- O-lOkc k- 0- 1 00 cps ELECTRICAL CHARACTERISTICS % TEST PROCEDURE / \ CAPACITIVE LOADING Capacitive loading characteristics of an operational amp- lifier are critical to the amplifier's system stability margin. Distributed capacitance that may occur in trunk lines, patch panel contacts, read out equipment, etc., can effect a marginally stable amplifier. Equally important, the large capacitive loading imposed by electronic mode control will To evaluate the amplifier's capacitive loading capabilities, it is necessary to plot stability as a function of summing junction load (Cs) versus output load (Co). TEST RESULT / \ I 1 r- T 0 .3 I 3 OUTPUT uf AMPLIFIER BALANCE Amplifier balance for chopper stabilized amplifiers is gen- erally accepted as the potentional between the output and summing junction. When the amplifier is balanced, in effect the summing junction offset is biased such that the summing junction (and output) potential is brought as close as pos- sible to system ground potential. Summing junction offset is usually the largest contributing factor to Integrator drift; thus amplifier balance is highly important if accurate in- tegration Is to be expected. SPECIFICATIONS Linear operating range ±13 3 v Output current § ±I0V DC ±33 ma Open Loop Gain (at DC) 4 x 10^ (at 100 cps) 40,000 (at I KC) 6,000 Bandwidth (-3db w/IOk-lOk) 350 KC (-3db w/IOOk-IOOk) 175 KC Phase shift (100 cps w/ I Ok- I Ok) 008° (Ike w/IOk-lOk) 05° (100 cps w/ 1 00k- 1 00k) 02° (Ike w/IOOk-IOOk) 20° Total Dynamic Error (IKC, 20vpp w/ I Ok- I Ok) 1% Velocity Limit 2 x 10® v/sec Output Noise (Full bandwidth I Ok- I Ok) 200 uv peak 125 uv RMS (Full bandwidth w/IOOk-IOOk) 800 uv peak 500 uv RMS Recovery from Saturated Overload 1.0 sec Input Current I 0 * ’ 2 amp Offset at the Summing Junction 0-3 uv Capacitive Loading on Output to ground (w/ 1 00k- 1 00k) I uf Capacitive Loading at summing junction to ground (w/IOOk-IOOk) 001 uf Stability - Feedback resistance o-c« Stability - Input resistance 500 ohms-